1. Field of the Invention
The present invention relates to a semiconductor device, especially to a method of fabricating metal oxide semiconductor transistor (MOSFET).
2. Description of the Prior Art
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in the semiconductor technologies. As the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues such as short channel effect and, the generation of parasitic capacitance, etc.
Recent advance in Si ULSI technology creates the need of low power devices operated at low supply voltage. The conventional CMOS device has been designed with thin gate-oxide and short effective channel length and hence this design strategy increases the gate to drain capacitance. Minimizing parasitic capacitance is a key issue for realizing high speed low-power ULSIs as mentioned in the reference "H. Nakamura et al., Symp. on VLSI Tech. Dig.,p.67,1995". This effect has reduced by utilizing a Gate-side Air-gap Structure (GAS) as seen in "M. Togo et al., Symp. on VLSI Tech. Dig.,p.38, 1996". The fringing field capacitance (CFR) becomes more important as the gate length is reduced to deep submicron as seen in "M. Togo et al., Symp. on VLSI Tech. Dig.,p.38, 1996". However, it is difficult to reduce the value of CFR, due to the difficulty of scaling down the dielectric spacer thickness as well as scaling down the device dimension.
To achieve the low voltage operation with small threshold voltage, the surface channel PMOSFET with the P+ poly gate has been investigated in place of the buried channel with the N+poly gate due to the superior short channel behavior as suggested in "B. Davari, in IEDM Tech. Dig., p.575,1996". However, the effect of boron penetration through the thin gate oxide into Si substrate will degrade the device performance. Please see the reference "A. Hori, et al. In IEDM Tech. Dig.,p.575 1996".